Random Access Memory (“RAM”) is a form of data storage that is used in modem computing devices and other electronic devices to store information. RAM can be embodied in a dedicated RAM chip that has as its only purpose the storage of information, or it can be part of a chip or circuit that has other functions, such as a system-on-a-chip that has RAM, a processor and other elements on a chip. While not intending any limitation to particular examples, RAM examples herein will assume that the RAM is present on a chip (or a plurality of chips) where the chip is made using semiconductor processing techniques or other techniques to all for information to be written to the RAM and later read back out of the RAM.
RAM is generally understood to be only capable of storing its contents while some power is applied to the RAM chip. “Storage” is a process that might encompass accepting data and address locations, writing that data to the specified address locations, maintaining some state of the RAM chip and/or the data, receiving read requests for data from address locations specified in the read requests and outputting that data. Preferably, unless there is a power interruption, the data read from a given address location of a RAM chip is the same as the data written to that address location with greater than some probability.
For a RAM to have storage capability, it has some structures that store data/stage. This can be through the use of electronic devices or elements, such as transistors, capacitors, and the like. Some RAM is referred to as Dynamic Random Access Memory (“DRAM”), in that the information is stored in devices or elements that need to be maintained or refreshed in order to hold onto the stored data. For example, in some modes of operation, a DRAM stores information as charge on a capacitor and the charge is maintained until power is removed or the charge is changed during a write operation. Information can be read and/or written using a transistor coupled with the capacitor.
In a known DRAM chip, there are a number of addressable data cells and each data cell comprises one transistor and one capacitor. This is often referred to as a 1-transistor-1-capacitor (1T1C) DRAM data cell. To store one bit of data into a 1T1C DRAM cell, the capacitor is charged to one of two signal levels, with the particular one of the two signal levels determined by the bit being written to the cell. Without loss of generality, when one bit is being referenced, the two possible values for the bit are referred to as “0” and “1”.
To read a value of the DRAM cell, the cell is connected to a bitline BL and to a word line WL. During sensing, the cell capacitance is connected to a much larger BL capacitance and the resulting attenuated cell signal on the BL is compared by a sensitive differential sense amplifier with a similarly attenuated reference voltage obtained, as an example, from a similar BL having no activated cells. The amplified cell signal can then be stored back into the cell. This operation is often called the “refresh” operation. Refresh operations are necessary in a DRAM since the capacitors used to store the information exhibit leakage and therefore need to be refreshed to guarantee the integrity of the data stored. In such a scheme, storing the data “0” can correspond to the voltage level Vss whereas storing the data “1” could correspond to the voltage level Vdd, with Vss typically being a higher voltage level relative to Vdd. Of course, this relationship is not required. The voltage levels might be referred to by values relative to a ground plane, or some other circuit or chip reference. In many examples herein, voltages are relative to Vss and for clarity, this is not specified each time. Thus, when voltages are referred to as numbers or quantities, it might be that Vss=0. Unless otherwise indicated, the units for such numbers or quantities are volts, but other scales might be used instead.
Two parameters of importance in the design of a DRAM are the “density” and the energy consumption. The density of a DRAM can be described by the number of bits that can be stored in a given unit of area. Generally, DRAMs of higher density are preferred over DRAMs of lower density because of the smaller packaging, and several other economic advantages. A large portion of the energy consumption of a DRAM is spent in the “refresh” operation whereby the information in each cell is read, amplified, and written back to the cell. This refresh operation is necessitated by the fact that the capacitors used to store information have small capacitance because of their physical size, and hence lose charge over time. Because of process variations of the electronic components used in a DRAM, the refresh interval, i.e., the amount of time passed between two successive refreshes of a cell, has to be short enough so that the worst cells still have not lost their information at the time of refresh. According to the standards set forth by the “Joint Electron Devices Engineering Council” (JEDEC), DRAM manufacturers need to make sure that the process variations which their devices are subject to are such that with the refresh interval of 64 ms (milliseconds), their devices do not lose data (with some level of certainty).
The response of the DRAM industry to the problem of storage density has been mostly confined to feature size reduction due to process technology improvements, reduction of the footprint of a storage cell, and sometimes other approaches such as 3D-stacking. Feature size and footprint reduction need to obey the rule that the cell size has to be F2 or larger, wherein F is the so-called minimum feature size and depends on the process technology used. A process technology of 32 nm, for example, has 32 nm as the value of F. DRAM units in use today have a cell size equal to 6*F2. Experimental designs have been reported that reduce this size even further, but reducing cell size is still a big challenge for the industry.
FIG. 1 is an exemplary block diagram schematic of a DRAM device 100 that is a conventional DRAM storage device. DRAM device 100 comprises a column decoder 130, I/O buffers 120, sense amplifiers 145, row decoders 110, and a memory area 140. Memory area 150 contains a plurality of actual memory cells. The memory cells are connected, via bitlines 133, to sense amplifiers 145 and column decoder 130, and, via wordlines 150, to row decoders 110. One of the memory cells in memory area 140 is indicated as memory cell 135 in FIG. 1 shown by a circle at an intersection of one wordline and one bitline. Although not shown explicitly, there can be connections between I/O buffers 120 and other elements of DRAM device 100, and there can be inputs of DRAM device 100 that are for row decoders 110 and outputs of DRAM device 100 that are for column decoder 130.
In operation, to write to a memory cell in response to DRAM device 100 receiving an input comprising the value to be written and a memory location to be written to, DRAM device 100 conveys the memory location (or at least part of it) to row decoders 110, which then activates one of wordlines 150 and DRAM device 100 conveys part of the memory location to column decoder 130, which then activates one or more of bitlines 133. DRAM device 100 might store the data temporarily in I/O buffers 120 and then move the data into the selected memory cell(s) via sense amplifiers 145. DRAM device 100's on-board logic (not explicitly shown) can charge the cell capacitance or discharge it, using the bitlines and the wordlines, based on the data to be written.
FIG. 2 provides an expanded view of memory cell 135, showing additional structure. Memory cell 135 is shown comprising a transistor 230 and a capacitor 250. Parts of a bitline 133(i) and a wordline 150(j) are shown and in this example, memory cell 135 is in row j and column i of memory area 140. Transistor 230 is shown coupled to bitline 133(i), wordline 150(j) (at the gate of transistor 230), and capacitor 250. The other side of capacitor 250 can be coupled to a ground, a reference, or elsewhere.
Capacitor 250 stores a charge that corresponds to the data state of the data stored in memory cell 135. During a write operation, when wordline 150(j) is activated (by row decoders 110; see FIG. 1), transistor 230 turns on and charge from bitline 133(i) transfers to capacitor 250. The charge stored in memory cell 135 is used to determine the “value” stored therein. Memory cell 135 can be read by activating wordline 150(j) and sensing the charge on capacitor 250 using bitline 133(i).
FIG. 3 illustrates a memory circuit where pre-charging is used. FIG. 3 shows portions of two memory arrays, with a first memory array 300 coupled to wordlines 302(1)-(3) and bitlines 320(a)-(c), and a second memory array 301 coupled to wordlines 312(1)-(3) and bitlines 330(a)-(c). Bitlines 320(a)-(c) and bitlines 330(a)-(c) are coupled to corresponding sense amplifiers 350(a)-(c), i.e., bitline 320(a) and bitline 330(a) are inputs to sense amplifier 350(a) and so on.
With bitlines 320 pre-charged to Vdd/2, bitlines 330 will be read by opening wordlines 312 and the difference of the charge to the pre-charged values of bitlines 320 are measured by sense amplifiers 350. These readings are then forwarded to row decoders (not shown) for obtaining the bit values in each cell. Thus, in conventional DRAM, each memory cell stores a charge in its associated capacitor and outputs a charge from the associated capacitor that corresponds directly to the value of the data received by the DRAM's I/O buffers and output from the I/O buffers.
The measurements of the charges in each cell are done with respect to the fixed reference Vdd/2. This has some significant implications. One of the implications is that the charges in the cells cannot fall below Vdd/2 if appropriate data state is to be reliably and repeatedly determined, and a suitable threshold depends on the sensitivity of the sense amplifiers.
The voltage read, Vr, from the capacitor at time t in a typical model, can be expressed as in Equation 1, wherein V is the original voltage applied to the capacitor, t is the time passed since the original voltage was applied, α is a decay parameter, and τ is a normal random variable modeling the process variation of the cells.
                    Vr        =                  V          ⁢                                          ⁢                      ⅇ                          -                                                t                  α                                τ                                                                        (                  Eqn          .                                          ⁢          1                )            
From Equation 1, it should be apparent that memory cells storing a greater charge in their capacitor decay faster than cells storing a smaller charge. To guarantee the integrity of the DRAM device, appropriate refresh intervals are therefore necessary.
This constraint is more significant for multilevel DRAMs, where information is stored as more than two charge levels. In multilevel DRAMs, the decay between some levels is faster than others and refreshing needs to take into account these variations. Note that, per Equation 1, the charge on the capacitor would go from Vdd to below Vdd/2, for example, in about the same time that it needs to drop, for example, from Vdd/2 to below Vdd/4.